| Rule Violations |
Count |
| Clearance Constraint (Gap=0.15mm) (All),(All) |
0 |
| Clearance Constraint (Gap=0.6mm) (IsRegion or InPoly),(InNet('PA02_ADC0') or InNet('PA03_ADC1_VREF') or InNet('NetCS300_1') or InNet('PB06_QTBTN1_SLCDX1') or InNet('PA20_GPIO_S2_4_RTS') or InNet('PA21_GPIO_S2_3_CTS') or InNet('PB08_PWM_TC0_0') or InNet('PB09_PWM_TC0_1') or InNet('PC02_GPIO_IRQ10') or InNet('PC03_GPIO_SS') or InNet('PA23_S2_1_UART_RX') or InNet('PA22_S2_0_UART_TX') or InNet('PB04_GPIO_SLCDY2') or InNet('PB05_GPIO_SLCDY1') or InNet('PA27_PWM_TCC0_5_SLCDY0')) |
0 |
| Clearance Constraint (Gap=0.119mm) (Touchesroom('EDBG_ROOM_1')or InComponent('U200')),(All) |
0 |
| Clearance Constraint (Gap=0.175mm) (InPoly),(All) |
0 |
| Clearance Constraint (Gap=0.6mm) (IsRegion),(InDifferentialPairClass('All Differential Pairs')) |
0 |
| Short-Circuit Constraint (Allowed=No) (All),(All) |
0 |
| Un-Routed Net Constraint ( (All) ) |
0 |
| Width Constraint (Min=0.125mm) (Max=1mm) (Preferred=0.15mm) (TouchesRoom('EDBG_ROOM_1')) |
0 |
| Width Constraint (Min=0.15mm) (Max=1mm) (Preferred=0.15mm) (All) |
0 |
| Routing Via (MinHoleWidth=0.25mm) (MaxHoleWidth=0.5mm) (PreferredHoleWidth=0.25mm) (MinWidth=0.55mm) (MaxWidth=1mm) (PreferedWidth=0.55mm) (All) |
0 |
| Routing Via (MinHoleWidth=0.2mm) (MaxHoleWidth=0.5mm) (PreferredHoleWidth=0.25mm) (MinWidth=0.4mm) (MaxWidth=1mm) (PreferedWidth=0.55mm) (TouchesRoom('EDBG_Room_1') Or InComponent('U200')) |
0 |
| Routing Via (MinHoleWidth=0.2mm) (MaxHoleWidth=0.5mm) (PreferredHoleWidth=0.25mm) (MinWidth=0.4mm) (MaxWidth=1mm) (PreferedWidth=0.55mm) (InDifferentialPairClass('All Differential Pairs')) |
0 |
| Differential Pairs Uncoupled Length using the Gap Constraints (Min=0.2mm) (Max=0.22mm) (Prefered=0.2mm) and Width Constraints (Min=0.18mm) (Max=0.18mm) (Prefered=0.18mm) (InDifferentialPair('EDBG_USB_HS') or InDifferentialPair('TARGET_USB')) |
0 |
| Differential Pairs Uncoupled Length using the Gap Constraints (Min=0.2mm) (Max=1.5mm) (Prefered=0.2mm) and Width Constraints (Min=0.12mm) (Max=0.18mm) (Prefered=0.18mm) (InDifferentialPair('EDBG_USB_FS')) |
0 |
| SMD Neck-Down Constraint (Percent=90%) (All) |
0 |
| Power Plane Connect Rule(Relief Connect )(Expansion=0.2mm) (Conductor Width=0.2mm) (Air Gap=0.2mm) (Entries=4) (HasFootprint('AP8-00257')) |
0 |
| Power Plane Connect Rule(Direct Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (IsVia OR HasPad('Free-666')) |
0 |
| Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All) |
0 |
| Assembly Testpoint Style (Under Component=Yes) (HasFootprint('AP8-00010') or HasFootprint('AP9-00044') or InNet('NetC407_1') or InNet('NetR105_2')) |
0 |
| Assembly Testpoint Style (Under Component=Yes) (All) |
3 |
| Assembly Testpoint Usage (Valid =Invalid, Allow multiple per net=No) (InNet('PA14')) |
0 |
| Assembly Testpoint Usage (Valid =Invalid, Allow multiple per net=No) (InNet('USB_P')) |
0 |
| Assembly Testpoint Usage (Valid =One Required, Allow multiple per net=No) (Disabled)(All) |
0 |
| Assembly Testpoint Usage (Valid =Invalid, Allow multiple per net=No) (InNet('XOUT0')) |
0 |
| Assembly Testpoint Usage (Valid =Invalid, Allow multiple per net=No) (InNet('XOUT32')) |
0 |
| Assembly Testpoint Usage (Valid =Invalid, Allow multiple per net=No) (InNet('NetCS700_1')) |
0 |
| Assembly Testpoint Usage (Valid =Invalid, Allow multiple per net=No) (InNet('USB_N')) |
0 |
| Assembly Testpoint Usage (Valid =Invalid, Allow multiple per net=No) (InNet('EDBG_USB_FS_N')) |
0 |
| Assembly Testpoint Usage (Valid =Invalid, Allow multiple per net=No) (InNet('PA15')) |
0 |
| Assembly Testpoint Usage (Valid =Invalid, Allow multiple per net=No) (InNet('XIN0')) |
0 |
| Assembly Testpoint Usage (Valid =Invalid, Allow multiple per net=No) (InNet('XIN32')) |
0 |
| Minimum Annular Ring (Minimum=0.1mm) (All) |
0 |
| Acute Angle Constraint (Minimum=70.000) (All) |
0 |
| Hole Size Constraint (Min=0.15mm) (Max=10mm) (All) |
0 |
| Pads and Vias to follow the Drill pairs settings |
0 |
| Hole To Hole Clearance (Gap=0.3mm) (All),(All) |
0 |
| Minimum Solder Mask Sliver (Gap=0.075mm) (All),(All) |
0 |
| Silk To Solder Mask (Clearance=0.075mm) (IsPad),(All) |
0 |
| Silk to Silk (Clearance=0mm) (IsText),(IsText) |
0 |
| Silk to Silk (Clearance=0.1mm) (All),(All) |
0 |
| Net Antennae (Tolerance=4mm) (Not Testpoint) |
1 |
| Room EDBG_ROOM_1 (Bounding Region = (195.445mm, 178.1mm, 202.655mm, 185.305mm) (All) |
1 |
| Component Clearance Constraint ( Horizontal Gap = 0mm, Vertical Gap = 0mm ) (InComponent('J206') or IsFree),(IsFree) |
0 |
| Component Clearance Constraint ( Horizontal Gap = 0.1mm, Vertical Gap = 0.1mm ) (All),(All) |
0 |
| Component Clearance Constraint ( Horizontal Gap = 0mm, Vertical Gap = 0mm ) (All),(InComponent('J900') or InComponent('J901') or InComponent('J902') or InComponent('J903') or InComponent('J904')) |
0 |
| Total |
5 |
